发明名称 Validating one or more circuits using one or more grids
摘要 In one embodiment, a method includes simulating by one or more computer systems a larger circuit to assign one or more values to one or more latch variables associated with the larger circuit, generating by the one or more computer systems one or more reduced circuits from the larger circuit according to the values assigned to the latch variables, generating by the one or more computer systems a transition relation (TR) for each reduced circuit, and generating by the one or more computer systems an initial state set for one or more instances of validation on the reduced circuits according to the TRs.
申请公布号 US8181132(B2) 申请公布日期 2012.05.15
申请号 US20090433182 申请日期 2009.04.30
申请人 JAIN JAWAHAR;IYER SUBRAMANIAN K.;PRASAD MUKUL R.;SIDLE THOMAS W.;FUJITSU LIMITED 发明人 JAIN JAWAHAR;IYER SUBRAMANIAN K.;PRASAD MUKUL R.;SIDLE THOMAS W.
分类号 G06F17/50 主分类号 G06F17/50
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