发明名称 Serial-connected memory system with output delay adjustment
摘要 Systems and methods for performing output delay adjustment are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if an output delay adjustment is needed. If so, the master device generates and outputs commands for the slave devices to perform output delay adjustment. The slave devices apply the output delay to the clock signal, but may also apply the delay to other output signals. Each of the slave devices has a circuit for performing output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.
申请公布号 US8181056(B2) 申请公布日期 2012.05.15
申请号 US20080241832 申请日期 2008.09.30
申请人 OH HAKJUNE;MOSAID TECHNOLOGIES INCORPORATED 发明人 OH HAKJUNE
分类号 G06F1/04;H04L7/00 主分类号 G06F1/04
代理机构 代理人
主权项
地址