| 摘要 |
PURPOSE: A data transmitting circuit is provided to transmit data at high speed by using a DDR(Double Data Rate) mode. CONSTITUTION: A reference clock generating unit has data output timing in rise transition timing and fall transition timing and generates a plurality of reference clocks with phase difference. A frequency divider(123) generates a transmission clock with a frequency corresponding to a phase difference between the plurality of reference clocks. A data output unit outputs data in a transition timing of a transmission clock. |
