| 摘要 |
Design apparatuses according to the present embodiments each include a CDFG generator, a scheduler, a binder, a retention register selector, a control circuit generator, and an RTL description generator. The binder generates a data path circuit in which a hardware element is allocated to a CDFG after scheduling by the scheduler. The retention register selector detects, as a retention control step, one of the control steps which has a minimum number of latch bits from the CDFG after scheduling and selects, as a retention register, a register allocated to the detected retention control step. The control circuit generator generates a control circuit which performs an execution control of the data path circuit and causes a state to transition to the retention control step when a signal for power-off is enabled. |
