| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an image reduction system capable of realizing, with a simple circuit configuration, a reduction process in which a reduction magnification is in the range of 1/1 to 1/2. <P>SOLUTION: The image reduction is performed at a reduction magnification of N/(N+j), where N is an exponentiation of 2, being 4 or larger, and j is an integer 1 to N. The pixel values of an output image are available by weighting interpolation calculation in which pixel values of input pixels stored in a first data register 112 and a second data resistor are multiplied with a coefficient generated by a coefficient generator using multipliers 122 and 123, with its results being added together using an adder 124. At the time of performing said weighting interpolation calculation, a division with N occurs, however, the division is performed by a right-shift process using the multipliers 122 and 123 or the adder 124. <P>COPYRIGHT: (C)2012,JPO&INPIT |
