发明名称 CHIP-INTEGRATED THROUGH-PLATING OF MULTILAYER SUBSTRATES
摘要 The invention relates to a method for producing a laminate (1, 11) for making contact with at least one electronic component (6, 16), in which an insulating layer (4, 14) is arranged between a first metal layer (2, 12) and a second metal layer (3, 18), electrical contact is made between the metal layers in at least one contact region, a recess is produced in the insulating layer in the contact region or recesses are produced in the contact regions, at least one embossed portion and/or at least one bulge is/are produced in the contact region at least in the first metal layer, wherein the distance between the two metal layers is reduced in the regions of the at least one embossed portion and/or bulge, the metal layers are laminated to the insulating layer, wherein the dimensions of at least one embossed portion and/or of at least one bulge suffice to accommodate at least one electronic component, at least one electronic component is inserted into at least one embossed portion and/or at least one bulge and is conductively connected there, with the result that the full extent of the electronic component is accommodated and the component is at least partially accommodated in the embossed portion or the bulge on the basis of the height (H) of the electronic component. The invention also relates to a laminate for making contact with an electronic component, in particular a laminate produced using such a method.
申请公布号 WO2012059186(A1) 申请公布日期 2012.05.10
申请号 WO2011EP05304 申请日期 2011.10.21
申请人 HERAEUS MATERIALS TECHNOLOGY GMBH & CO. KG;OSRAM OPTO SEMICONDUCTORS GMBH;KLEIN, ANDREAS;DITZEL, ECKHARD;KRUEGER, FRANK;SCHUMANN, MICHAEL 发明人 KLEIN, ANDREAS;DITZEL, ECKHARD;KRUEGER, FRANK;SCHUMANN, MICHAEL
分类号 H05K1/18;H01L23/498;H01L33/60;H01L33/62;H05K3/40 主分类号 H05K1/18
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