发明名称 DEBUGGING DEVICE AND DEBUGGING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a debugging device and a debugging method that improve debugging efficiency. <P>SOLUTION: The debugging device includes an instruction execution section (32), a register (24), a trace memory (22), and a bus control section (38). The instruction execution section (32) executes a program code to output an address to be accessed to a bus (IBUS/PBUS). The program code includes a dedicated debug code used for debugging, and the instruction execution section (32) outputs a control signal (dummy read execution signal) indicating that the debug code is being executed. The register (24) holds an address set by a host device (10). The trace memory (22) stores data indicative of the state of the bus (PBUS). The bus control section (38) outputs the address set in the register (24) to the bus instead of the address that the instruction execution section (32) outputs when a control signal (DSTB) is active. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012088839(A) 申请公布日期 2012.05.10
申请号 JP20100233596 申请日期 2010.10.18
申请人 RENESAS ELECTRONICS CORP 发明人 NISHIMURA SHUNJI
分类号 G06F11/28 主分类号 G06F11/28
代理机构 代理人
主权项
地址