| 摘要 |
A processor comprising groups of plural processor elements and corresponding data registers. When a first operating mode is selected, distinct data to be calculated is written to the data registers of the groups. The same data is written to the data registers of at least two groups when a second mode is selected. Calculation results from the groups are selectively outputted, and comparison between two groups outputs is made. Selection and comparison of calculation results are carried out when the first and second modes are set, respectively. Calculation results are outputted when they agree with each other; otherwise an error is produced. |
