| 摘要 |
<P>PROBLEM TO BE SOLVED: To eliminate race condition due to clock skew without employing an expensive circuit equipped with a clock line whose phase is compensated. <P>SOLUTION: Provided are a plurality of data holding units 10a-10n, which receive data in synchronization with clock to hold them, and auxiliary data holding units 20b-20n, provided corresponding to a part or the whole of data holding units 10b-10n respectively and receive data to be received next by the paired data holding units 10b-10n, at a data receiving timing different from the data holding units 10b-10n to hold them while the data holding units 10b-10n provides a synchronizing circuit for receiving data from the auxiliary data holding units 20b-20n respectively. <P>COPYRIGHT: (C)2009,JPO&INPIT |
