| 摘要 |
<p>The electronic circuit has a selecting device and three pulse signal paths. The selecting device is arranged to connect the former pulse signal path with either of the other two pulse signal paths. One of the three pulse signal paths is provided with multiple delay elements (31a-35a). Two of the three pulse signal paths are connected with a common clock pulse input (11). A common section is provided in which the delay elements are arranged.</p> |
