发明名称 Method for facilitating the stacking of integrated circuits having different areas and an integrated circuit package constructed by the method
摘要 An integrated circuit package comprises a package substrate, an application specific integrated circuit (ASIC) having a first area and formed on a first wafer made from a select semiconductor material, a second wafer of the select semiconductor material, and a supplemental-integrated circuit. The supplemental-integrated circuit has a second area different from the first area. The first wafer includes a through-wafer via to couple the ASIC to the package substrate. An active surface of the ASIC is coupled to the second wafer. The second wafer is arranged with a window there through that is sized to closely receive and align one or more bonding interfaces of the supplemental-integrated circuit to respective bonding interfaces of the ASIC. A corresponding method for assembling a die-stacked integrated circuit package is disclosed.
申请公布号 US8174108(B2) 申请公布日期 2012.05.08
申请号 US20100730947 申请日期 2010.03.24
申请人 O'NEILL PETER MARK;AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE.LTD. 发明人 O'NEILL PETER MARK
分类号 H01L23/02 主分类号 H01L23/02
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