| 摘要 |
The present invention introduces a sub-converter stage used in a pipelined analog-to-digital converter. The sub-converter stage comprises an amplifier with a gain A, a sub analog-to-digital converter with comparators and a digital unit, a first capacitor with capacitance C, a second capacitor with capacitance C−ΔC, and customized reference signal Vrefk, whereΔ C C = 4 A + 2 and V refk = V ref ( 1 -Δ C 2 C ) . If the gain A of the amplifier is adjustable, the sub-converter stage needs an error detector to detect the difference between the output of the amplifier and reference signal Vref and adjust the gain A of the amplifier. The present invention also introduces a pipelined analog-to-digital converter employing the sub-converter stage. In the pipelined analog-to-digital converter and the sub-converter stage presented by this invention, the error generated by the finite gain of amplifier and the error generated by the capacitance mismatch have the same size but opposite sign, ending that the two errors can compensate each other. As a result, the sub-converter stage achieves an error-free conversion and the two errors are calibrated.
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