Low power, single poly EEPROM cell with voltage divider

摘要

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider (804) is coupled in series with the switch. A sense transistor (152) has a sense control terminal (156) and a current path coupled between an output terminal (108) and a reference terminal (110). A first capacitor (154) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor (716) has a control terminal coupled to receive a read signal (721), and a current path coupled between the output terminal and a bit line (718).