发明名称 System and method for testing a memory
摘要 A computer system comprising a processor, a memory, and a memory controller coupled to the processor and the memory is provided. The memory controller comprises a first cache and a cache control. The cache control is configured to cause a portion of the memory to be copied into the first cache. The cache control is configured to cause first information to be provided from the first cache to the processor in response to receiving a read transaction from the processor that includes an address in the portion of memory during testing of the portion.
申请公布号 US8176250(B2) 申请公布日期 2012.05.08
申请号 US20030652536 申请日期 2003.08.29
申请人 SHIDLA DALE J.;BARR ANDREW H.;POMARANSKI KEN G.;HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 SHIDLA DALE J.;BARR ANDREW H.;POMARANSKI KEN G.
分类号 G06F12/00;G06F12/08;G06F11/00;G06F11/22;G06F12/16;G11C29/08;G11C29/56 主分类号 G06F12/00
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