发明名称 Multi-domain management of a cache in a processor system
摘要 A system and method are provided for managing cache memory in a computer system. A cache controller portions a cache memory into a plurality of partitions, where each partition includes a plurality of physical cache addresses. Then, the method accepts a memory access message from the processor. The memory access message includes an address in physical memory and a domain identification (ID). A determination is made if the address in physical memory is cacheable. If cacheable, the domain ID is cross-referenced to a cache partition identified by partition bits. An index is derived from the physical memory address, and a partition index is created by combining the partition bits with the index. A processor is granted access (read or write) to an address in cache defined by partition index.
申请公布号 US8176282(B2) 申请公布日期 2012.05.08
申请号 US20090419139 申请日期 2009.04.06
申请人 BOUVIER DANIEL L.;APPLIED MICRO CIRCUITS CORPORATION 发明人 BOUVIER DANIEL L.
分类号 G06F12/08;G11C8/00 主分类号 G06F12/08
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