发明名称 Cache used both as cache and staging buffer
摘要 In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
申请公布号 US8176257(B2) 申请公布日期 2012.05.08
申请号 US201113087974 申请日期 2011.04.15
申请人 WADHAWAN RUCHI;KASSOFF JASON M.;YIU GEORGE KONG;APPLE INC. 发明人 WADHAWAN RUCHI;KASSOFF JASON M.;YIU GEORGE KONG
分类号 G06F13/00;G06F12/00 主分类号 G06F13/00
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