发明名称 Voltage boosting/lowering circuit
摘要 A voltage boosting/lowering circuit in accordance with present invention includes an output voltage generation circuit including a first switch element connected between an input terminal and one end of a choke coil and a second switch element connected between the other end of the choke coil and a ground terminal, the output voltage generation circuit being configured to boost or lower an input voltage input to the input terminal and thereby to generate an output voltage by switching the first and second switch elements between an On-state and an Off-state. Further, voltage boosting/lowering circuit includes a clock generation circuit that generates voltage-boosting and voltage-lowering clocks having different timings, and a switch control unit that performs switching control of the first and second switch elements based on the voltage-boosting and voltage-lowering clocks so that negative feedback control is performed so as to bring the output voltage to a target output voltage.
申请公布号 US8174249(B2) 申请公布日期 2012.05.08
申请号 US20100914701 申请日期 2010.10.28
申请人 UCHIIKE TAKESHI;RENESAS ELECTRONICS CORPORATION 发明人 UCHIIKE TAKESHI
分类号 G05F1/24 主分类号 G05F1/24
代理机构 代理人
主权项
地址