METHOD FOR FORMING STRESS ISOLATION TRENCH SEMICONDUCTOR DEVICE

摘要

A method for forming a stress isolation trench semiconductor device is provided. The method comprises: providing a silicon substrate (S11); forming at least two parallel first trenches in the silicon substrate, and forming a first dielectric layer in the first trenches, wherein the first dielectric layer is a tensile dielectric layer (S12); forming at least two parallel second trenches in the silicon substrate, and forming a second dielectric layer in the second trenches, wherein the extending direction of the second trenches is perpendicular to that of the first trenches (S13); and after forming the first trenches, forming a gate stack in the silicon substrate between the adjacent first trenches, wherein the direction of the channel length under the gate stack is parallel to the extending direction of the first trenches, index of crystallographic plane of the silicon substrate is {100} and the first trenches extend along the direction of the crystal orientation <110> (S14). The tensile stress is provided in the direction of the channel width of a MOS transistor, so as to improve the performance of a PMOS transistor and/or an NMOS transistor.