DEFECT AND YIELD PREDICTION FOR SEGMENTS OF AN INTEGRATED CIRCUIT

摘要

Defect prediction information is determined for a segment of an integrated circuit layout. Marker information is obtained, for example from user input into a computer design tool, where the marker information defines the segment. A segment can be defined to be any arbitrary portion of the layout and can include portions of multiple blocks. The marker information is used to extract layout information corresponding to the segment. The extracted segment layout information is analyzed to determine the defect prediction information. In one example, the determination involves performing a Critical Area Analysis such that the defect prediction information is a yield prediction value. This process is repeated for multiple segments, and the defect prediction information for the segments is compared to identify the segment most susceptible to defects. The user can modify the design of the segment, and repeat the process to improve yield in the manufacture of the integrated circuit.