发明名称 CONNECTION VERIFICATION METHOD, RECORDING MEDIUM THEREOF, AND CONNECTION VERIFICATION APPARATUS
摘要 A connection verification method is disclosed. A computer verifies a connection between a first node and a second node by starting from the first node in a designed integrated circuit, based on connection information stored in a storage part. The computer detects whether a module connected to the second node is a predetermined module predetermined module having a logic condition therein, based on connection relationship logic information stored in the storage part. The computer conducts a connection verification starting the module to verify a connection between the module and a third node when the module is the predetermined module.
申请公布号 US2012110527(A1) 申请公布日期 2012.05.03
申请号 US201113280961 申请日期 2011.10.25
申请人 MATSUBARA SATOSHI;KUROKAWA AKIRA;FUJITSU SEMICONDUCTOR LIMITED;FUJITSU LIMITED 发明人 MATSUBARA SATOSHI;KUROKAWA AKIRA
分类号 G06F17/50 主分类号 G06F17/50
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