发明名称 PCI express address translation services invalidation synchronization with TCE invalidation
摘要 A PCI Express (PCIe) computer system utilizes address translation services to translate virtual addresses from I/O device adaptors to physical addresses of system memory. A combined memory controller and host bridge uses a translation agent to convert the I/O addresses via translation control entries (TCEs) in a TCE table (also known as an address translation and protection table). Some of the I/O device adaptors have address translation caches for local storage of TCEs. The TCE definition includes a new non-cacheable control bit which is set active in the TCE table when the TCE is in the process of being invalidated. The memory controller prevents further caching of the TCE while the non-cacheable control bit is active. A further implementation utilizes a change-in-progress control bit of the TCE to indicate that the TCE is in the process of being changed to allow simultaneous invalidation of the previously TCE information.
申请公布号 US8171230(B2) 申请公布日期 2012.05.01
申请号 US20070949078 申请日期 2007.12.03
申请人 FREIMUTH DOUGLAS M.;RECIO RENATO J.;THURBER STEVEN M.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 FREIMUTH DOUGLAS M.;RECIO RENATO J.;THURBER STEVEN M.
分类号 G06F12/00;G06F9/26;G06F9/34;G06F13/00;G06F13/28 主分类号 G06F12/00
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