| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a system having a main controller and a plurality of semiconductor devices connected in series, where each device stores data, and the controller supplies a clock for synchronizing operation of the devices. <P>SOLUTION: Each device has a PLL which is enabled or disabled selectively by an enable signal. The PLL of a selected device is enabled by an enable signal and other devices are disabled. An enabled PLL supplies a plurality of reproduction clocks with phase shift equal to a multiple of 90°. Data transfer is synchronized with one of reproduced clocks. In the device of a disabled PLL, data transfer is synchronized with an input clock. By the enabled and disabled PLL, each device performs source synchronization clocking and common synchronization clocking. Lowermost bit of the device identifier of the last device determines clock arrangement. <P>COPYRIGHT: (C)2012,JPO&INPIT |
