发明名称 |
SHIELDING TECHNIQUES FOR AN INTEGRATED CIRCUIT |
摘要 |
Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches. |
申请公布号 |
US2012098104(A1) |
申请公布日期 |
2012.04.26 |
申请号 |
US20100911171 |
申请日期 |
2010.10.25 |
申请人 |
JIN YONGGANG;STMICROELECTRONICS PTE. LTD. |
发明人 |
JIN YONGGANG |
分类号 |
H01L23/544;H01L21/302;H01L21/78 |
主分类号 |
H01L23/544 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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