| 摘要 |
A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced. There are included a counter for performing a counting operation synchronized with a reference clock signal: a timing memory for outputting respective data corresponding to the quotient and remainder resulting from dividing the time from the front of a basic period until a generation of a timing edge by the period of the reference clock signal: a coincidence detecting circuit for outputting a signal that exhibits a high level when the count value of the counter coincides with the quotient: a jitter generating circuit for outputting as a jitter amplitude value: adders for adding a time corresponding to the remainder and a time represented by the jitter amplitude value outputted from the jitter generating circuit: and a variable delay circuit for delaying the output signal from the coincidence detecting circuit by the time represented by the addition result of the adders and outputting the delayed output signal.
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