| 摘要 |
A semiconductor memory apparatus includes a memory block including memory strings having respective channel layers coupled between respective bit lines and a source line, an operation circuit group configured to supply hot holes to the channel layers and to perform an erase operation on memory cells of the memory strings, an erase operation determination circuit configured to generate a block erase enable signal when hot holes of at least a target number are supplied to a first channel layer of the channel layers, and a control circuit configured to perform the erase operation in response to the block erase enable signal. |
