发明名称 SWITCHED CAPACITOR CIRCUIT, SAMPLE AND HOLD CIRCUIT, AND A/D CONVERTER
摘要 <P>PROBLEM TO BE SOLVED: To obtain a switched capacitor circuit in which the superiority that it is adaptable even to an input signal of relatively large amplitude is maintained while limiting a required level on the operating speed of an operational amplifier applied to a switched capacitor circuit using CLS technology. <P>SOLUTION: A CLS circuit 120 is configured to include a capacitor Ccls and switches SW104, SW105, and SW106, while a changeover circuit 130 is configured of a conductor having an interposed switch SW 107 and SW 104, SW 105, and SW 106. Connection relation is switched by the changeover circuit 130 so that the capacitor Ccls for level shift is connected to be charged with an analog input signal Vin in the sampling phase, and interposed between an analog signal output terminal Vb and the output terminal of an operational amplifier 110 in the level shift phase. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012085133(A) 申请公布日期 2012.04.26
申请号 JP20100230259 申请日期 2010.10.13
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 SANO MITSUHIRO
分类号 H03K5/08;H03F3/34;H03M1/12 主分类号 H03K5/08
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