发明名称 SEMICONDUCTOR MEMORY AND SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To surely read data by surely turning on or off an amplification transistor according to the logic of data held in a real memory cell. <P>SOLUTION: A selection transistor and a resistance variable element of a real memory cell are connected in series between a first voltage line and a second voltage line through a connection node. A real amplification transistor of the real memory cell has a gate, a source, and a drain connected to a connection node, a reference voltage line, and a real read line respectively. In a reading operation, the gate of the selection transistor receives a read control voltage, and a desired voltage is generated in the connection node by resistance division between the selection transistor and the resistance variable element. A sense amplifier determines a logic held in the real memory cell according to a voltage of the real read line varied with a voltage generated in the connection node. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012084202(A) 申请公布日期 2012.04.26
申请号 JP20100229310 申请日期 2010.10.12
申请人 FUJITSU LTD 发明人 AOKI MASAKI
分类号 G11C11/15;G11C13/00 主分类号 G11C11/15
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