| 摘要 |
A method, system and computer program product are provided for implementing enhanced net routing with improved correlation of pre-buffered and post-buffered routes on a hierarchical design of an integrated circuit chip. In initial wiring steps the nets are routed, and then buffers are add along the net route based upon predetermined electrical parameters. Responsive to adding the buffers, distance based constraints are added to the nets. Then the nets that have been modified are rerouted. |
