| 摘要 |
<P>PROBLEM TO BE SOLVED: To enhance tolerance for error. <P>SOLUTION: An LDPC code having a code length of 4320 bits is written in the column direction of a memory 31, and read in the row direction. The code bits of 2, 4 or 6 bits read from the memory 31 are mapped, as one symbol, to 2<SP POS="POST">2</SP>, 2<SP POS="POST">4</SP>or 2<SP POS="POST">6</SP>signal points. As rearrangement processing for rearranging the code bits of the LDPC code so that a plurality of code bits corresponding to 1 in any one row of the check matrix of the LDPC code are not contained in one symbol, a column twist interleaver performs column twist interleave for changing the start of writing position when the code bits are written in the column direction of the memory 31 for each column of the memory 31. The invention is applicable to transmission of the LDPC code. <P>COPYRIGHT: (C)2012,JPO&INPIT |
