发明名称 Asymetric layout structures for transistors and methods of fabricating the same
摘要 High power transistors are provided. The transistors include a source region (13), a drain region (17) and a gate contact (24). The gate contact (24) is positioned between the source region (13) and the drain region (17). First and second ohmic contacts (20,22) are provided on the source and drain regions (13,17), respectively. The first and second ohmic contacts (20,22) respectively define a source contact (20) and a drain contact (22). The source contact (20) and the drain contact (22) have respective first and second widths. The first and second widths are different. Related methods of fabricating transistors are also provided.
申请公布号 EP2445010(A2) 申请公布日期 2012.04.25
申请号 EP20120151832 申请日期 2005.08.25
申请人 CREE, INC. 发明人 SRIRAM, SAPTHARISHI;HENNING, JASON
分类号 H01L29/417;H01L21/335;H01L21/338;H01L29/778;H01L29/812 主分类号 H01L29/417
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