发明名称 |
Reducing the latency of sum-addressed shifters |
摘要 |
The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time. |
申请公布号 |
US8166085(B2) |
申请公布日期 |
2012.04.24 |
申请号 |
US20080105726 |
申请日期 |
2008.04.18 |
申请人 |
DHONG SANG HOO;JACOBI CHRISTIAN;MUELLER SILVIA MELITTA;NISHIKAWA HIROO;OH HWA-JOON;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DHONG SANG HOO;JACOBI CHRISTIAN;MUELLER SILVIA MELITTA;NISHIKAWA HIROO;OH HWA-JOON |
分类号 |
G06F15/00;G06F7/38 |
主分类号 |
G06F15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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