发明名称 |
Memory circuits, systems, and method of interleaving accesses thereof |
摘要 |
An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell. |
申请公布号 |
US8164974(B2) |
申请公布日期 |
2012.04.24 |
申请号 |
US20100698423 |
申请日期 |
2010.02.02 |
申请人 |
HSU KUOYUAN;HUANG MING-CHIEH;KIM YOUNG SUK;KENGERI SUBRAMANI;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HSU KUOYUAN;HUANG MING-CHIEH;KIM YOUNG SUK;KENGERI SUBRAMANI |
分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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