发明名称 TIMING CIRCUIT AND METHOD OF GENERATING OUTPUT TIMING SIGNAL
摘要 <P>PROBLEM TO BE SOLVED: To provide a timing circuit and a corresponding method for generating an output timing signal in dependence on an input timing signal. <P>SOLUTION: The timing circuit is configured to receive an input timing signal and generate an output in dependence on the input. Each circuit component switches its output level in response to a transition of its input level and exhibits a delay in switching its output level, and the delay includes a first delay associated with a first switching of its output level and a second delay associated with a second switching. The first switching is in an opposite direction to the second switching, and the first and second delays exhibit a change in magnitude as the switching operations are repeatedly performed. This change in magnitude is in opposite directions for the first delay and the second delay respectively, and a timing of the output signal is dependent on both the first delay and the second delay such that the effects of each on the timing of the output signal counteract one another. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012080532(A) 申请公布日期 2012.04.19
申请号 JP20110196880 申请日期 2011.09.09
申请人 ARM LTD 发明人 NICOLAAS CLARINUS JOHANNES VAN VINKENHOF;SEBASTIEN NICOLAS RICAVY;GERALD JEAN LOUIS GUYA
分类号 H03K5/00;G11C11/4076 主分类号 H03K5/00
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