发明名称 |
Double Patterning Technology Using Single-Patterning-Spacer-Technique |
摘要 |
A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing. |
申请公布号 |
US2012091592(A1) |
申请公布日期 |
2012.04.19 |
申请号 |
US20100907640 |
申请日期 |
2010.10.19 |
申请人 |
CHEN HUANG-YU;HSIEH KEN-HSIEN;OU TSONG-HUA;FAN FANG-YU;HOU YUAN-TE;SHIEH MING-FENG;LIU RU-GUN;LU LEE-CHUNG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHEN HUANG-YU;HSIEH KEN-HSIEN;OU TSONG-HUA;FAN FANG-YU;HOU YUAN-TE;SHIEH MING-FENG;LIU RU-GUN;LU LEE-CHUNG |
分类号 |
H01L29/41;G03F1/00;G03F7/20;G06F17/50;H01L21/283 |
主分类号 |
H01L29/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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