发明名称 |
INTELLIGENT ARCHITECTURE CREATOR |
摘要 |
Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. |
申请公布号 |
US2012096420(A1) |
申请公布日期 |
2012.04.19 |
申请号 |
US20100906857 |
申请日期 |
2010.10.18 |
申请人 |
PANDURANGAN ANAND;NG PIUS;SELVARAJ SIVA;BANERJEE SANJAY;DURBHA ANANTH;KADIYALA SURESH;PADMANABHAN SATISH |
发明人 |
PANDURANGAN ANAND;NG PIUS;SELVARAJ SIVA;BANERJEE SANJAY;DURBHA ANANTH;KADIYALA SURESH;PADMANABHAN SATISH |
分类号 |
G06F9/455;G06F17/50 |
主分类号 |
G06F9/455 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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