| 摘要 |
1295294 Adaptive processors TEXAS INSTRUMENTS Inc 30 Sept 1969 [23 Dec 1968] 48006/69 Heading G4R In an adaptive non-linear processor there is provided a number of "linear" units, or a single "linear" unit common to a number of subcircuits, these units generating weighting functions which minimize, in a least mean square sense, the error between the output signal of the processor and the desired output in response to an input signal. During a learning mode successive pairs of traning signals are applied to the processor, each pair comprising an input signal u and the corresponding desired output z of the processor. The signals are quantized and applied to the linear units to develop and store the weighting functions. In the subsequent recognition mode modification of the functions by input signals to be recognized is prevented. Linear unit Fig. 7.-Weighting values 1a(j), 2a(j) are stored on capacitors 74, 78. These values, which may be zero initially, are fed back to multipliers 60, 67 via delays 79, 80 for multiplication respectively with the present value u (j+l) of the input signal to the non-linear processor and with the previous value x (j) of the processor's output. During the learning mode the multiplier outputs are added at 63 and the result subtracted at 65, 66 from the desired output z (j +l) of the processor in response to the input u (j+l). The output of adder 66 is muliplied at 69, 70 with the present input u (j+l) and the previous output x (j), the results being added at 72, 74, to the previous weighting values 1a (j) 2a (j) to provide updated weighting values 1a (j+l), 2a (j+l) to capacitor stores 74, 76. During the recognition mode switches 64a, 69a, 70a are open so that the stored weighting values can not be modified. Non-linear processor.-An input signal u (j +l) from source 10, Fig. 8, and Fig. 5 (not shown), passes to quantizer 11, Fig. 3 (not shown), which delivers an output on one of four leads to enable a corresponding column of gates 90 in a matrix of 16 gates. The output x (j+l) of the processor passes to delay 206 which delivers a signal x (j) to quantizer 14. Quantizer 14 enables the gates 90 in one of the four rows of the matrix. Signals x (j) and u (j+l) therefore select one of the gates. In one embodiment, Fig. 5 (not shown), each gate 90 is associated with a corresponding linear unit 92 shown in Fig. 7 and enables gate 81 to pass the various signals to the unit. The weighting values 1a (j+l), 2a (j+l) from the selected linear unit are then multipled with x (j) and u (j+l) and the results added by multipliers and an adder common to all the linear units to give the processor output x (j+l). In a second embodiment, Fig. 8, a signal linear unit 92 is used, the stores 74, 78 and delays 79, 80, Fig. 7, being replaced by stores 220, 221 and delays 224 at each point in the gate matrix. The output x (j+l) is then formed from the weighting values in the selected stores, x (j) and u (j+l) by the multipliers 60, 67 and adder 63 in the linear unit rather than by the common adder and multiplers in the first embodiment. Specification 1,264,387 is referred to. |
