Arithmetisch-logische Einheit

摘要

1,081,665. Data processors. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 21, 1966 [April 5, 1965], No. 12255/66. Heading G4A. In a data-processing device, a logical function of corresponding portions of two operands is formed and passed through first or second means to an output register, the first means providing the result of an arithmetic operation on the operands and the second performing an operation. Two operands are fed to a bit function generator which produces the AND, OR and OR-E (meaning exclusive-or) of each pair of corresponding bits. For addition, the output of a final sum adder is gated to an output register, the final sum adder being fed with half sums (being the OR-E signals), and carries from a carry look-ahead generator fed by the AND and OR signals. Subtraction is by one's or two's complement addition, involving the inversion of one of the operands before input to the bit function generator, and control of the carry look-ahead generator either to permit end-around carry or to add 1 to the lowest order bit position respectively. For shift, the set of bits to be shifted and a set of all zeroes are supplied as the two operands and the OR-E signals (equalling the bits to be shifted) are gated to the shifter from which (after shifting) they are gated to the output register. The results of the logical operations AND, OR, OR-E are passed to the output register via the shifter (without shifting) by passing to the shifter the AND, AND and OR-E, OR-E signals from the bit function generator respectively. It is mentioned that the shift function may be used in multiplication or division (but no details are given.