| 摘要 |
<p>In accordance with an exemplary embodiment, an apparatus is provided for selecting among asynchronous clocks and for generating a clock without glitch to the output. The apparatus comprises two or more synchronizer units (410a, 420a, 410b, 420b), each connected to an assigned clock signal (401a, 401 b). Each synchronizer unit (410a, 420a, 410b, 420b) receives a clock select signal (403) and a status signal of the other clock(s) (461a, 461 b). It generates a synchronized enable request signal (41 1a, 41 1 b) and a synchronized status signal of the other clock(s) (421a, 421 b) to a processor or a state machine (440a, 440b). In response to the synchronized enable request signal (41 1a, 41 1 b) and the synchronized status signal of the other clock(s) (421a, 421 b), the processor (440a, 440b) generates an enable signal (441 a, 441 b) to a clock gate (480a, 480b) and a status output signal to the other synchronizer unit(s). The enable signal (441 a, 441 b) controls the clock gate (480a, 480b) which enables or disables the clock signal to an output.</p> |
