| 摘要 |
<P>PROBLEM TO BE SOLVED: To allow prevention of reverse engineering via a debug terminal. <P>SOLUTION: A debug terminal control circuit 3 extracts a validation routine R1 from a debug program P1 executed by a CPU 4 and controls a debug terminal 2, based on the extracted validation routine R1, so as to input a debug input signal S4 received by the debug terminal 2 to the CPU 4. Consequently, when an external memory 7a stores the debug program P1, the debug terminal 2 is validated and the debug input signal S4 is input to the CPU 4, but when the external memory 7a does not store the debug program P1, the debug terminal 2 is invalidated and the debug input signal S4 is not input to the CPU 4. As a result, invalidation of the debug terminal 2 at shipment allows prevention of reverse engineering via the debug terminal 2. <P>COPYRIGHT: (C)2012,JPO&INPIT |
