| 摘要 |
With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption. |
