发明名称 |
Gate electrode in a trench for power MOS transistors |
摘要 |
A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region. |
申请公布号 |
US8159025(B2) |
申请公布日期 |
2012.04.17 |
申请号 |
US20100683014 |
申请日期 |
2010.01.06 |
申请人 |
TANG MING;CHIAO SHIH-PING;PTEK TECHNOLOGY CO., LTD. |
发明人 |
TANG MING;CHIAO SHIH-PING |
分类号 |
H01L29/66;H01L21/336 |
主分类号 |
H01L29/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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