发明名称 Method and system for sizing polygons in an integrated circuit (IC) layout
摘要 One embodiment of the present invention provides a system that sizes a polygon in a layout. During operation, the system receives a polygon which is to be sized by a sizing amount. The system then selects one or more vertices of the polygon. Next, the system replaces each selected vertex with a set of replacement vertices, and subsequently assigns a projection path to each replacement vertex in the set of replacement vertices. The system next performs a sizing operation on the polygon according to the sizing amount. During the sizing operation, the system moves each replacement vertex in the set of replacement vertices along the assigned projection path, thereby creating a clipping on the angle associated with the selected vertex. Furthermore, this sizing operation is continuous: similar output polygons are obtained for similar sizing amounts.
申请公布号 US8161426(B2) 申请公布日期 2012.04.17
申请号 US20090363159 申请日期 2009.01.30
申请人 MORALES DOMINGO;BAYTELMAN FELIPE;ARAYA HUGO;SYNOPSYS, INC. 发明人 MORALES DOMINGO;BAYTELMAN FELIPE;ARAYA HUGO
分类号 G06F17/50 主分类号 G06F17/50
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