发明名称 CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE
摘要 A block interleaver (610) for interleaving blocks of coded symbols comprises a 2-dimension word addressable DWA memory. An M-row-by-N-column array (610) of bit cells (300) is addressed by logic (242, 252) using 2-Dimension Addressing, using first and second orthogonal address spaces. The block interleaver accepts the coded symbols in blocks by filling the columns of the array, and outputs the interleaved symbols one row at a time. A corresponding de-interleaver, and ping-pong buffer (600) comprising an interleaver and de-interleaver, are disclosed.
申请公布号 KR101114695(B1) 申请公布日期 2012.04.17
申请号 KR20107001695 申请日期 2008.06.26
申请人 发明人
分类号 G06F12/02;G11C8/04 主分类号 G06F12/02
代理机构 代理人
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