发明名称 |
Reset mechanism conversion |
摘要 |
Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed. |
申请公布号 |
US8161435(B2) |
申请公布日期 |
2012.04.17 |
申请号 |
US20090505653 |
申请日期 |
2009.07.20 |
申请人 |
MANOHAR RAJIT;KELLY CLINTON W.;EKANAYAKE VIRANTHA;PAUL GAEL;ACHRONIX SEMICONDUCTOR CORPORATION |
发明人 |
MANOHAR RAJIT;KELLY CLINTON W.;EKANAYAKE VIRANTHA;PAUL GAEL |
分类号 |
G06F17/50;H01L25/00;H03K19/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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