发明名称 METHOD FOR FABRICATING BURIED BIT LINE OF VERTICAL TRANSISTOR
摘要 PURPOSE: A method for fabricating a buried bit line of a vertical transistor is provided to ensure the stability and reliability of a device by improving a contact resistance characteristic of a buried bit line which is contacted with a drain region. CONSTITUTION: A trench(215) is formed on a semiconductor substrate(200). A liner film(220) is formed on the substrate on which the trench is formed. The liner film is selectively eliminated and an open area is formed. A polysilicon layer is formed on the liner film. A metal layer is formed on the polysilicon layer. A silicide metal film is formed between the polysilicon layer and a metal layer. A buried bit line(275), which recesses the silicide metal film and fills a part of the trench, is formed.
申请公布号 KR20120035497(A) 申请公布日期 2012.04.16
申请号 KR20100097036 申请日期 2010.10.05
申请人 SK HYNIX INC. 发明人 HA, GA YOUNG
分类号 H01L21/8242;H01L21/28;H01L27/108 主分类号 H01L21/8242
代理机构 代理人
主权项
地址