发明名称 OPTIMIZING EXIT LATENCY FROM AN ACTIVE POWER MANAGEMENT STATE
摘要 A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.
申请公布号 KR101129748(B1) 申请公布日期 2012.04.13
申请号 KR20087031574 申请日期 2004.12.23
申请人 发明人
分类号 G06F1/32;G06F1/26 主分类号 G06F1/32
代理机构 代理人
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