发明名称 Area Efficient Selector Circuit
摘要 A signal converting system has a multi-segment digital to analog converter coupled to an error shaping loop. A control value is received at a vector processor that indicates a number N of elements that are to be selected from a vector having M elements. The elements of the vector are sorted into a bitonic sequence and separated into a larger value group and a smaller value group using a bitonic split. Only the larger value group is sorted into an ordered sequence with repeated bitonic splits when the control value is less than M/2, and N largest elements are selected from the ordered sequence. Only the smaller value group is sorted into an ordered sequence with repeated bitonic splits when the control value is greater than M/2, and N−M/2 largest elements are selected from the ordered sequence.
申请公布号 US2012086591(A1) 申请公布日期 2012.04.12
申请号 US20100902493 申请日期 2010.10.12
申请人 SURYONO YANTO 发明人 SURYONO YANTO
分类号 H03M3/00;G06F9/02;G06F15/76;H03M1/66 主分类号 H03M3/00
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