| 发明名称 |
METHOD OF MANUFACTURING VIA ELECTRODE |
| 摘要 |
Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles. |
| 申请公布号 |
US2012086132(A1) |
申请公布日期 |
2012.04.12 |
| 申请号 |
US201113267215 |
申请日期 |
2011.10.06 |
| 申请人 |
KIM DONG-PYO;BAEK KYU-HA;PARK KUNSIK;PARK JI MAN;KIM ZIN SIG;KIM JOO YEON;JEONG YE SUL;DO LEE-MI;ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
KIM DONG-PYO;BAEK KYU-HA;PARK KUNSIK;PARK JI MAN;KIM ZIN SIG;KIM JOO YEON;JEONG YE SUL;DO LEE-MI |
| 分类号 |
H01L23/48;B82Y40/00;B82Y99/00;H01L21/02;H01L21/768 |
主分类号 |
H01L23/48 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
