发明名称 Modular Programmable Delay Line Blocks for Use in a Delay Locked Loop
摘要 Modular delay line blocks include a plurality of delay elements, each including a delay unit, an input, an output, a next element output, and an element return path. The delay elements are coupled together in a chain between a block input and a block output. The block input is coupled to the input of a first element in the chain and the block output is coupled to the output of the first element. In addition, the next element output of the first element is coupled to the element input of a next element in the chain, and the element output of the next delay element is coupled to the element return path of a previous element in the chain. In response to a selection control signal, each element may selectively route a signal from the element input to one of the next element output or to the element output.
申请公布号 US2012086485(A1) 申请公布日期 2012.04.12
申请号 US20100901778 申请日期 2010.10.11
申请人 TRIVEDI PRADEEP R.;VON KAENEL VINCENT R. 发明人 TRIVEDI PRADEEP R.;VON KAENEL VINCENT R.
分类号 H03L7/06;H03H11/26 主分类号 H03L7/06
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