发明名称 |
IN-PLACE RESYNTHESIS AND REMAPPING TECHNIQUES FOR SOFT ERROR MITIGATION IN FPGA |
摘要 |
In-place resynthesis for static memory (SRAM) based Field Programmable Gate Arrays (FPGAs) toward reducing sensitivity to single event upsets (SEUs). Resynthesis and remapping are described which have a low overheard and improve FPGA designs without the need of rerouting LUTs of the FPGA. These methods include in-place reconfiguration (IPR), in-place X-filling (IPF), and in-place inversion (IPV), which reconfigure LUT functions only, and can be applied to any FPGA architecture. In addition, for FPGAs with a decomposable LUT architecture (e.g., dual-output LUTs) an in-place decomposition (IPD) method is described for remapping a LUT function into multiple smaller functions leveraging the unused outputs of the LUT, and making use of built-in hard macros in programmable-logic blocks (PLBs) such as carry chain or adder. Methods are applied in-place to mapped circuits before or after routing without affecting placement, routing, and design closure. |
申请公布号 |
WO2012047735(A2) |
申请公布日期 |
2012.04.12 |
申请号 |
WO2011US54096 |
申请日期 |
2011.09.29 |
申请人 |
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA;HE, LEI;LEE, JU-YUEH;FENG, ZHE;JING, NAIFENG |
发明人 |
HE, LEI;LEE, JU-YUEH;FENG, ZHE;JING, NAIFENG |
分类号 |
H03K19/177;G06F17/50 |
主分类号 |
H03K19/177 |
代理机构 |
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